The present invention relates to a semiconductor design technology, and more particularly, to technology for detecting data stored in a nonvolatile memory cell.
Phase change random access memory (PCRAM) is a representative nonvolatile memory device that programs memory cells by using a programming current.
PCRAM having a nonvolatile memory characteristic can provide a random access, and can be highly integrated at low cost. PCRAM stores data by using a phase change material. To be specific, PCRAM is a nonvolatile memory device using a phase change of a phase change material depending on a temperature condition, that is, a resistance change depending on a phase change.
A phase change material is changeable to an amorphous state or a crystalline state according to a temperature condition. A representative phase change material is a chalcogenide alloy. Since a typical example of the phase change material is Ge2Sb2Te5 containing germanium (Ge), antimony (Sb), and tellurium (Te), the phase change material is called a “GST”.
PCRAM causes a reversible phase change between a crystalline state and an amorphous state of the phase change material by using Joule heat generated by applying a specific current or voltage to the phase change material. The crystalline state is called a set state in terms of circuit. In the set state, the phase change material has an electrical characteristic like a metal with a low resistance. The amorphous state is called a reset state in terms of circuit. In the reset state, the phase change material has a resistance higher than in the set state. That is, PCRAM stores data on the basis of a resistance change between the crystalline state and the amorphous state, and determines the stored data by detecting a current flowing through the phase change material or a voltage change depending on a current change. In general, the set state is defined as having a logic level “0” and the reset state is defined as having a logic level “1”. The phase change material maintains its state even when power is interrupted.
Meanwhile, a programming current can make the phase change material change from the crystalline state to the amorphous state, and vice versa. A set current is defined as a programming current that changes the phase change material of the memory cell to the set state, and a reset current is defined as a programming current that changes the phase change material of the memory cell to the reset state. The set current and the reset current are also called a set programming current and a reset programming current, respectively.
If the reset current is supplied to heat the phase change material for a certain time at a temperature higher than a melting temperature, the phase change material cools rapidly and changes to the amorphous state. Also, if the set current is supplied to heat the phase change material for a certain time at a temperature higher than a crystallization temperature and lower than a melting temperature, the phase change material cools slowly and changes to the crystalline state. Meanwhile, since a resistance value is differentiated according to the crystalline volume or the amorphous volume of the phase change material, a multi-level memory cell can be implemented. In general, the reset current is made to flow with a large current for a relatively shorter time than the set current, and the set current is made to flow with a small current for a relatively longer time than the reset current. That is, the state of the phase change material is changed by Joule heating generated under a specific condition by the supply of the programming current.
FIG. 1 is a circuit diagram of a conventional phase change memory device.
Referring to FIG. 1, a phase change memory device includes a phase change memory cell 110, a data sense amplifier 120, and a switch 130. That is, FIG. 1 illustrates the structure of the phase change memory device that performs a data read operation to detect data of the phase change memory cell 110.
The phase change memory cell 110 includes a cell diode D1 and a phase change element GST. The cell diode D1 has a cathode connected to a word line WL, and an anode connected to a first node N0. The phase change element GST is connected between a bit line BL and the first node N0.
The data sense amplifier 120 supplies a data detection current to the phase change memory cell 110 and detects a data detection voltage having a voltage level corresponding to a resistance of the phase change memory cell 110. The data sense amplifier 120 includes a data detection current supplying unit MP0 and a voltage comparing unit 121. The data detection current supplying unit MP0 supplies the data detection current, and the voltage comparing unit 121 compares the data detection voltage with a reference voltage VREF.
The switch is implemented with a PMOS transistor MP1 and selectively transfers the data detection current outputted from the data sense amplifier 120 to the phase change memory cell 110.
An operation of detecting data programmed into the phase change memory cell 110 will be described below.
When a word line WL, a read signal RD, and a selection signal SEL are all activated to low level in a data read mode, the data detection current outputted from the data detection current supplying unit MP0 is supplied to the phase change memory cell 110 through a PMOS transistor MP1. The cell diode D1 of the phase change memory cell 110 is forward-biased, the cell diode D1 is turned on from the moment when a voltage difference between the anode and the cathode of the cell diode D1 is larger than a threshold voltage (Vth). In this case, when the phase change element GST of the phase change memory cell 110 is in the amorphous state, it has a high resistance and thus a voltage level of a second node N1 rises. On the contrary, when the phase change element GST of the phase change memory cell 110 is in the crystalline state, it has a lower resistance than in the amorphous state and thus the voltage level of the second node N1 falls. Accordingly, the voltage comparing unit 121 of the data sense amplifier 120 detects the data stored in the phase change memory cell 110 by comparing the reference voltage VREF with the voltage of the second node N1.
Meanwhile, the phase change memory device of FIG. 1 has superior data detection performance when the phase change element GST of the phase change memory cell 110 is in the amorphous state (data “1). However, the data detection performance of the phase change memory device is relatively degraded when the phase change element GST is in the crystalline state (data “0”). That is, since the switch 130 is implemented with the PMOS transistor MP1, a voltage difference (VGS) between a gate and a source of the PMOS transistor MP1 becomes smaller as the voltage level of the second node N1 is lower. Thus, if the voltage difference (VGS) between the gate and the source of the PMOS transistor MP1 is lower than the threshold voltage (Vth), a resistance of the PMOS transistor MP1 increases and consequently the PMOS transistor MP1 is turned off. Therefore, if the voltage level of the second node N1 becomes lower than a certain value, the data detection voltage corresponding to the resistance of the phase change element GST is not transferred to the second node N1. In such a case, even though the resistance of the phase change memory cell 110 is low, the voltage of the second node N1 does not reflect it. That is, performance in the detection of data “0” is degraded.